The present invention generally relates to a receiver architecture for use with Code Division Multiple Access (CDMA) and spread spectrum wireless networks.
Code Division Multiple Access (CDMA) refers to any of several protocols used in so-called second-generation (2G) and third-generation (3G) wireless communications. CDMA is a form of multiplexing that allows numerous signals (channels) to occupy a single physical transmission channel, thereby optimizing bandwidth. These signals, a re transmitted using the same frequency band and are differentiated by transmitting each signal using a different spreading code. The spreading codes are orthogonal to each other. This property enables separate signals to be transmitted simultaneously from a transmitter (e.g., a base station) since a CDMA receiver can distinguish between these signals by correlating each received signal against a given spreading code. In a similar fashion, scrambling codes are used to distinguish between different base stations. In particular, each base station uses a different scrambling code for scrambling all of the transmitted signals. A scrambling code covers a radio frame (38,400 chips) and comprises 38,400 chip values. Accordingly, spreading codes allow individual signals to be differentiated, whereas scrambling codes allow signals from different base stations to be differentiated.
In practice, multiple delayed versions of the transmitted signal arrive at a CDMA receiver (e.g., a cellular handset). For example, one version of the signal may arrive by traveling a direct path from the base station to a cellular handset, while another version of the signal may arrive later because the signal reflected off of a building before arriving at the CDMA receiver. As such, the received signal is known as a multipath signal and contains multiple delayed versions of the transmitted signal, where each version of the transmitted signal is known as a path.
During decoding, the CDMA receiver processes the received multipath signal to identify the various paths contained therein. This function typically is performed by a system or logic block referred to as a “searcher”. The searcher identifies individual paths of the multipath signal by correlating received samples against different offsets of a scrambling code, which is previously identified by the CDMA receiver from the received multipath signal. Notably, a correlator, or a processor that performs correlation, can demodulate a spread spectrum signal and/or measure the similarity of an incoming signal against a reference. The correlations are performed for a given dwell time such as 128, 256, or 512 chips over a corresponding portion of the scrambling code. By adjusting the offset of the portion of the scrambling code used for correlation, the searcher can perform correlations at different time delays to determine the particular delays at which valid paths exist.
The searcher generates a profile, which is a vector of the correlation output at different time delays. This profile is examined to determine the delays of the multipath signal at which various paths are located. This information can be passed to a rake receiver portion of the CDMA receiver. A rake receiver uses several baseband correlators, referred to as fingers, to individually process several paths of a multipath signal in accordance with the determined delays. In any case, the individual outputs of the rake receiver are combined to achieve improved communications reliability and performance.
A searcher typically is one of the largest blocks in a CDMA receiver, and is inefficient with respect to hardware design and power consumption. One reason for this is that a conventional searcher utilizes hardware-implemented linear feedback shift registers (LFSRs) to generate different offsets of the scrambling code. In particular, an LFSR generates a portion of the scrambling code dynamically, or “on the fly”, with a new scrambling code chip value being generated for each chip in the dwell time. In addition, the CDMA receiver requires one finger to extract each path. Accordingly, one LFSR is needed for each individual finger since each finger operates at a different phase/delay of the scrambling code.
Conventional searcher architectures have other inefficiencies as well. For example, typically a series of multiplexers are used to access each of the output registers of the various descramblers in the searcher architecture. This configuration often leads to an inefficient implementation that reduces the overall speed at which the hardware operates. In addition, while conventional designs use multiple descramblers to allow the processing of multiple received signals simultaneously, such configurations do not provide for the generation of multiple values per chip.
It would be advantageous to provide a hardware-efficient design for a searcher for use in a CDMA receiver that overcomes the deficiencies described above.